1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to power supply switching circuit.
2. Description of Related Art
A semiconductor memory includes the type in which a memory cell is constituted of an electrically writable and erasable floating gate field effect transistor.
Referring to FIG. 1, there is shown a diagrammatic sectional view of this type memory cell. As shown in FIG. 1, the memory cell includes a P-type semiconductor substrate 11 and a drain diffused region 12 and a source diffused region 13 formed separately from each other by selectively ion implanting arsenic into a principal surface of the substrate. Furthermore, a floating gate 14 and a control gate 15 are stacked through an insulator film on the principal surface of the substrate between the drain region 12 and the source the region 13. An insulating film 16 is formed to cover the whole of the memory cell.
In the case of writing information into this memory cell, a high voltage on the order of 12V is applied to the gate electrode 15, and a high voltage of the order of 6 V is applied to the drain 12, and the source 13 is grounded so that electrons are injected to the floating gate by action of a hot carrier injection, with the result that a threshold voltage viewed from the floating gate 15 is made high.
FIG. 2 is a graph illustrating an initial condition (non-written condition) and the written condition of this type memory cell. In the non-written condition, the memory cell becomes conductive by applying a control gate voltage Vcg on the order of 2 V, as shown by the curved line 21. On the other hand, in the non-written condition, the memory cell becomes conductive by applying a control gate voltage Vcg on the order of 6 V, as shown by the curved line 22.
Accordingly, if the control gate voltage is set to 5 V, the memory cell in the non-written condition is brought into a conductive condition, but the memory in the written condition is maintained in a non-conductive condition. Information is memorized by a difference of the current between the conductive condition and the non-conductive condition.
In the above mentioned semiconductor memory, in the case of reading the information, the semiconductor memory is operated with a power supply voltage of 5 V, and in the case of writing the information, it is necessary to selectively supply the memory cell gate with the high voltage of for example 12 V, which is supplied from an external circuit of the semiconductor memory, or is generated by a step-up circuit internally provided in the semiconductor memory. Therefore, a power supply switch circuit is required which selectively switch between the power supply voltage of 5 V at the information reading time and the high voltage of 12 V at the information writing time.
Referring to FIG. 3, there is shown a circuit diagram of one example of a prior art power supply switching circuit. In addition, the following TABLE 1 shows a DC voltage on various nodes in the circuit shown in FIG. 3.
TABLE 1 ______________________________________ G.sub.1 G.sub.2 G.sub.3 G.sub.4 V.sub.out ______________________________________ V.sub.pp (12 V) V.sub.cc (5 V) 0 V 0 V V.sub.cc (5 V) 0 V 0 V V.sub.cc (5 V) V.sub.pp (12 V) V.sub.pp (12 V) ______________________________________
As shown in FIG. 3, the prior art power supply switching circuit includes a pair of P-channel metal oxide semiconductor field effect transistors (each simply called "PMOSFET" hereinafter) MP1 and MP2 are connected in series between a writing high voltage Vpp and an output terminal Vout. A substrate potential of the PMOSFET MPI is connected to the writing high voltage Vpp, and a substrate potential of the PMOSFET M2 is connected to the output terminal Vout. The prior art power supply switching circuit also includes another pair of PMOSFETs MP3 and MP4 are connected in series between a reading voltage Vcc and the output terminal Vout. A substrate potential of the PMOSFET MP3 is connected to the reading voltage Vcc, and a substrate potential of the PMOSFET MP4 is connected to the output terminal Vout.
Now, a DC operation of the shown prior art power supply switching circuit will be described with reference to the TABLE 1, assuming that 2 V is supplied as the writing high voltage Vpp and 5 V is supplied as the reading voltage Vcc.
In the case of outputting 5 V from the output terminal Vout, 0 V is applied to gate terminals G3 and G4 of the PMOSFETs MP3 and MP4, so as to render these PMOSFETs MP3 and MP4 conductive, so that the reading voltage Vcc is transferred throlgh the PMOSFETs MP3 and MP4 to the output terminal Vout. As a result, a voltage of the output terminal Vout becomes 5 V.
At this time, 12 V is applied to a gate G1 of the PMOSFET MP1 and 5 V is applied to a gate G2 of the PMOSFET MP2, so that the PMOSFETs MP1 and MP2 are brought into a non-conductive condition. Therefore, the writing high voltage Vpp is completely isolated from the output terminal Vout.
On the other hand, in the case of outputting 12 V from the output terminal Vout 0 V is applied to the gate terminals G1 and G2 of the PMOSFETs MP1 and MP2, so as to render these PMOSFETs MP1 and MP2 conductive, so that the writing high voltage Vpp is transferred through the PMOSFETs MPI and MP2 to the output terminal Vout. As a result, a voltage of the output terminal Vout becomes 12V.
At this time, 5 V is applied to the gate G3 of the PMOSFET MP3 and 12 V is applied to the gate G4 of the PMOSFET MP2, so that the PMOSFETs MP3 and MP4 are brought into a non-conductive condition. Therefore, the reading voltage Vcc is completely isolated from the output terminal Vout.
Thus, in the prior art power supply switching circuit as mentioned above, either the writing high voltage Vpp or the reading voltage Vcc is alternatively outputted, and there is no unnecessary DC current leakage. This is attributable to provision of the PMOSFETs MP2 and MP4.
Namely. when 12V is outputted from the output terminal Vout, since the gate terminal G4 of the PMOSFET MP4 is brought to 12V, the PMOSFET MP4 is brought into the non-conductive condition, so that the voltage of the utput terminal Vout is never applied to a connection node between the PMOSFETs MP3 and MP4.
Here, if it is assumed that the voltage of 12V is applied to the connection node B, a PN junction between a P-type diffusion layer of the PMOSFET MP3 at the side of the connection node B, and the substrate potential of the PMOSFET MP3 applied with 5 V, is biased in a forward direction, so that a leakage current occurs.
On the other hand, it is considered that when 5 V is outputted from the output terminal Vout, the writing high voltage Vpp is brought to OV, because, in an ordinary reading operation, 0 V is applied to a terminal of the writing high voltage Vpp from an external circuit of the semiconductor memory.
In this case, by applying 5 V to the gate G2 of the PMOSFET MP2, the PMOSFET MP2 is brought into the non-conductive condition, the voltage of the output terminal Vout is not applied to a connection node A between the PMOSFETs MPI and MP2.
Here, if t is assumed that the voltage of 5 V is applied to the connection node A, a PN junction between a P-type diffusion layer of the PMOSFET MP1 at the side of the connection node A, and the substrate potential of the PMOSFET MP1 applied with OV, is biased in a forward direction, so that a leakage current occurs.
Now, an AC operation of the shown prior art power supply switching circut will be described with reference to FIG. 4, which is a waveform diagram illustrating a change in voltage on various nodes in the circuit shown FIG. 3.
First, consider that the output voltage Vout is caused to change from 5V to 12 V. At a timing T1, the gate voltage G1 of the PMOSFET MP1 is caused to change from 12V to OV, and the gate voltage G2 of the PMOSFET MP2 is caused to change from 5V to OV, so that the PMOSFETs MP1 and MP2 are rendered conductive. On the other hand, the gate voltage G3 of the PMOSFET MP3 is caused to change from 0 V to 5 V, and the gate voltage G4 of the PMOSFET MP4 is caused to change from 0 V to 5 V, so that the PMOSFETs MP3 and MP4 are rendered non-conductive. Thus, the output terminal Vout is charged through the PMOSFETs MP1 and MP2, and reaches 12V at a timing T2.
In the above mentioned process of charging the output terminal Vout from 5 V to 12 V, since the P-type diffused layer of the PMOSFET MPt at the side of the writing high voltage Vpp and the substrate potential of the PMOSFET MP1 are 12 V, the voltage is supplied from the writing high voltage Vpp to the connection node A in an ordinary MOSFET operating condition. On the other hand, since the P-type diffused layer of the PMOSFET MP2 at the side of the connection node A is 12 V, and since the P-type diffused layer of the PMOSFET MP1 at the side of the output terminal Vout and the substrate potential of the PMOSFET MP2 are 5 V, a PN junction between the P-type diffused layer of the PMOSFET MP 2 at the side of the connection node A and the substrate potential of the PMOSFET MP 2 is biased in a forward direction.
An Operation condition of this MOSFET MP2 will be described with reference to FIG. 5, which is a diagrammatic section view of the PMOSFET MP2 formed in a P-type semiconductor substrate 1.
As shown in FIG. 5, an N-type well 2 is formed in the P-type semiconductor substrate 1, and the PMOSFET MP2 is constituted of a pair of P-type diffused layers 3 and 4 formed in the N-type well 2 and a gate electrode 7 located through a gate insulator (not shown) on a channel region defined between the pair of P-type diffused layers 3 and 4. Furthermore, an N-type diffused layer 5 is formed in the N-type well 2 for supplying a biasing voltage for the N-type well 2. As seen from comparison between FIGS. 3 and 5, the P-type diffused layer 3 is connected to the connection node A, and the P-type diffused layer 4 and the N-type diffused layer 5 is connected to the output terminal Vout.
A P-type diffused layer 6 is formed for supplying a ground potential GND to the P-type semiconductor substrate 1, and is connected to the ground potential GND.
In the structure shown in FIG. 5, if the N-type well 2 and the P-type diffusect layer 4 are brought to 5 V, and the P-type diffused layer 3 is brought to 12 V, a PN junction between the P-type diffused layer 3 and the N-type well 2 is biased in a forward direction, so that holes are injected from lie P-type diffused layer 3 to the N-type well 2. The holes, which have been injected into the N-type well 2 and which are minority carriers in the N-type well 2, reach the P-type diffused layer 4 by passing through a path I1, so that the holes are supplied to the output terminal Vout. As a result, the potential of the output terminal Vout elevates.
This means that a PNP junction constituted of the P-type diffused layer 3, the N ype well 2 and the P-type diffused layer 4, operates as a bipolar transistor. Thereafter, if the potential of the N-type well 2 elevates and the injection of the holes terminates, the PMOSFET MP2 operates as an ordinary MOSFET.
Furthermore, when the holes are injected from the P-type diffused layer 3, a PNJ junction constituted of the P-type diffused layer 3, the N-type well 2 and the P-type semiconductor substrate 1, also operates as a bipolar transistor. The holes are injected into the P-type semiconductor substrate 1, by passing through a path 12, and the holes injected into the P-type semiconductor substrate I are taken out through the P-type diffused layer 6.
On the other than, when the output terminal Vout is caused to change from 2 V to 5 V, an electric charge is discharged from the output terminal Vout through the PMOSFETs MP3 and MP4 to the reading voltage Vcc, so that the output voltage Vout is brought to 5 V. In this process, the P-type diffused layer of the PMOSFET MP3 at the side of the connection node B is biased in a forward direction, the PMOSFET MP3 operates is a bipolar transistor, similarly to the PMOSFET MP2 mentioned just above.
Incidentally, in order to shorten the period that the PMOSFET MP3 operates as the bipolar transistor, there is provided a means (not shown in FIG. 3) composed of an N-channel metal oxide semiconductor field effect transistor (simply called "NMOSFET" hereinafter) which is connected between the output terminal Vout and the ground GND and which is turned on for a predetermined period at an initial stage of the process of changing the output voltage Vout from 12V to 5 V, so that the charge of the output terminal Vout is further discharged.
As mentioned above, in the prior art power supply switching circuit as mentioned above, when the output voltage Vout is switched from 5 V to 12 V, in the period from TI to T2 in the timing chart of FIG. 4, the PMOSFET MP 2 operates as the bipolar transistor to charge the output terminal Vout. At this time, since the holes are simultaneously charged into the P-type semiconductor substrate, an unnecessary current flows from the writing high voltage Vpp, with the result that a consumed electric current inevitably increases.
This also means that when a load capacitance of the output voltage Vout is large, the period from TI to T2 in the timing chart of FIG. 4 becomes long. This is a serious problem.
Furthermore, there is dangerous possibility that the holes injected into the substrate causes a latch-up. Accordingly, this restricts a location of circuit elements in the neighborhood of the power supply switching circuit.
Other than the period of switching the output voltage Vout from 5 V to 12V, in a period of constantly outputting the output voltage Vout at 12 V or 5 V when a consumed current of a load circuit connected to the output Vout is large, since the output voltage Vout, namely, the substrate potential of the PMOSFETs MP2 and MP4 lower, the P-type diffused layer of the PMOSFET MP2 at the side of the connection node A in the case of outputting 5 V, and the P-type diffused layer of the PMOSPET MP4 at the side of the connection node B in the case of outputting 12 V, are biased in the forward direction with the result that holes are injected into the P-type semiconductor substrate. Accordingly, the consumed current increases, and there occurs dangerous possibility that the holes injected into the substrate causes a latch-up.